1. Field of the Invention
This invention pertains generally to the fabrication of semiconductor structures, and more particularly to a process for precision alignment and direct bonding of silicon based materials to mechanical, electrical, semiconductor and/or optical structures.
2. Description of the Background Art
Three dimensional semiconductor structures are commonly fabricated on substrates using conventional masking, doping and etching techniques to produce a monolithic structure. For example, a CMOS device is generally fabricated by forming both p-type and n-type channels on a p-type substrate. Some three dimensional structures, such as silicon on insulator devices, are fabricated by depositing a thin silicon film on an insulating sapphire substrate. While these techniques are suitable for many devices, some device technologies are highly complex, use incompatible processes, or suffer from undesirable parasitic elements when fabricated monolithically on a single substrate.
For example, it is difficult to fabricate monolithic npn and pnp bipolar transistors of high gain or speed on a single chip of semiconductor material. This results from the requirement that the base width and doping for either npn or pnp transistors must be carefully controlled to achieve high gain or speed. While it is relatively straightforward to carefully control either a p-type base in an npn or an n-type base in a pnp transistor, it is very difficult to achieve both in a single process sequence. The present invention overcomes this deficiency by allowing for fabrication of the npn and pnp portions of the structure on separate wafers where each transistor type can be optimized, and then providing for aligning and bonding the wafers to integrate the overall structure.
Non-aligned silicon direct bonding is a known technique which has been used in a "bond and etch back" process to create high purity silicon on insulator (SOI) material. The technique has been useful in bonding a single patterned wafer to bulk substrates to create working electrical and mechanical devices. However, a technique that allows for the precision alignment of two prefabricated surfaces with high accuracy has not been heretofore developed.
Device features consistent with electronic, optical or micromechanical structures often need to be bonded to a substrate material. Present techniques for bonding are limited to using adhesives which commonly suffer from contamination, or mechanical bonds such as solder pads. None of these techniques provide for critical alignment and bonding of the materials at the atomic level, wherein the bonds are similar to those within the crystals themselves and no additional adhesives are required. Therefore, there is a need for a process which permits independent fabrication of semiconductor structures and provides for subsequent precision aligned bonding for fabrication of an integrated device.